Key job responsibilities

Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
Being actively engaged in design-backend convergence aspects and defining timing constraints.
Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
Engaged in defining implementation and signoff methodologies.

A day in the life
Your day will be a dynamic blend of technical innovation and collaborative problem-solving. You'll dive deep into intricate chip design processes, working with state-of-the-art tools and technologies to create semiconductor solutions that drive cloud computing forward. Expect to engage in complex design challenges, collaborate with brilliant engineers, and see your work directly impact global technological advancement.
About the team
We are a passionate group of semiconductor experts dedicated to pushing the boundaries of cloud technology. Our team thrives on innovation, collaboration, and continuous learning. We value diverse perspectives and believe that breakthrough technologies emerge from inclusive, supportive environments where every team member can contribute their unique insights.
Basic Qualifications

8+ years of experience in physical design
Understanding the entire place and route flow ("RTL to GDS")
Very deep understanding of timing
Process and technology (advanced nodes) oriented
Leadership and mentoring skills

Preferred Qualifications

Full-chip experience (floor plan, layout, timing)
Previous experience in high-speed designs, multi-voltage (low power) designs

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