About the Role
We are seeking a Principal Verification Engineer to lead functional verification for complex SoC / IP architectures. You will collaborate across architecture, design, physical implementation, and software teams, driving verification methodology, execution, and closure.
Key Responsibilities

Analyse system and architecture specifications to define verification strategy.
Develop test and coverage plans for IP / SoC blocks.
Build and maintain scalable verification environments (SystemVerilog / UVM / SystemC / C++).
Create stimulus, assertions, checkers, trackers, and functional coverage.
Execute verification plans including bring-up regressions, debug, and coverage closure.
Develop and run test cases in SystemVerilog and embedded C.
Debug and root‑cause failures, working closely with design and architecture teams.
Manage verification deliverables across internal and external teams.
Mentor and guide junior verification engineers.

Required Experience

Master’s degree in a relevant discipline.
15+ years verification experience on complex SoC / IP.
Strong expertise in SystemVerilog / UVM and SystemC / C++.
Hands‑on experience with constrained‑random verification and functional coverage.
Debug experience across RTL, testbench, and integration issues.
Experience with Formal Verification and UPF.
HW / SW co‑verification and simulation experience.
Scripting experience (Bash, Perl, Python).
Strong communication and problem‑solving skills (English required).

Why Join
This is an opportunity to shape advanced SoC / IP solutions while mentoring the next generation of verification engineers in a technically ambitious environment. If you could be suitable for this position, please get in touch.
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