Mixed-Signal Verification Engineer (SystemVerilog/UVM)

Livorno 27-11-2025

Mixed-Signal Verification Engineer (SystemVerilog/UVM)

Apple Livorno 27-11-2025
Riassunto

Località

Livorno

Divisione Aziendale

Tipo di contratto

Data di pubblicazione

27-11-2025

Descrizione Lavoro

A leading technology company is seeking an experienced engineer to join their Analog Mixed Signal Design Verification Team. The role involves developing verification test plans, designing test benches, and collaborating with various teams to ensure compliance with system requirements. Candidates should have a Master’s in Electrical Engineering and hands-on experience with mixed signal verification tools. This position is full-time based in Livorno, Italy.
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