Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer.Job duties :Developing test plans, tests and verification infrastructure using SV / UVM methodologyBuilding reusable bus functional models, monitors, checkers and scoreboardsPerforming block level, multi-block level and system-level verificationPerforming Mixed Signal simulationsImplementing Regression testsWorking closely with IC designers and post-silicon engineersQualifications and BackgroundRequirements :Knowledge / experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creationKnowledge / experience in scripting languages, such as Tcl and PythonSome knowledge of ASIC design flow and related verification stepNice to have :Knowledge of UVM environments and classesSome experience with main EDA vendors simulators such as Questasim and XceliumKnowledge of DFT structures and test pattern generationSome experience in silicon validation / characterisationExperience working on Git.For more information, please contact Rob Hudson.Digital Engineer • Parma, Emilia Romagna
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